A semiconductor manufacturing process is a series of steps that make the various layers and structures of an integrated circuit. Each layer of the integrated circuit is made using one or more masks. A mask defines the features of the layer. To realize one of the layers, a semiconductor wafer is coated with a thin layer of liquid photosensitive resist (also called “photoresist” or simply “resist”).
FIG. 1 (Prior Art) is a diagram of a conventional wafer stepper that uses light. The wafer stepper projects laser light through a mask to expose parts of the photoresist and to leave other parts of the photoresist unexposed. Generally areas of photoresist that are exposed harden. The unhardened photoresist is washed away, leaving a pattern of hardened photoresist. The hardened areas of photoresist protect the underlying areas of the integrated circuit during a subsequent manufacturing step. After the subsequent manufacturing step has been performed, the hardened photoresist layer is stripped away. Another layer of liquid photoresist is applied to the integrated circuit being formed. In this way, a typical semiconductor manufacturing process uses many masks and many associated manufacturing steps.
Semiconductor manufacturing processes are generally referred to in terms of the smallest feature size that can be made using the process. A so-called 20 nm CMOS process can make a field effect transistor gate having a gate length of 20 nm. This 20 nm is the distance across the channel between the source and drain diffusion regions. This distance needs to be well controlled. Currently photolithographic techniques employing 193 nm wavelength light are usable to make 20 nm wide gates. Using such photolithography, it is possible to make 20 nm wide parallel strip-shaped features at 100 nm pitch, where the 100 nm pitch does not vary more than 1 nm. The width of each parallel strip is also well controlled along the length of the strip. A problem, however, exists when small corners of hardened photoresist are to be made, and when the ends of narrows strips of hardened photoresist are to be made. The wavelength of the laser light used to expose the photoresist through the mask is so large compared to the size of the corner, that light diffraction through the mask causes a large variation in edge definition. To cope with such edge definition problems in a 20 nm process, OPC (Optical Proximity Correction) techniques are generally used on each photoresist mask.
FIG. 2 (Prior Art) is a diagram that shows a desired structure 1 of hardened photoresist. This structure 1 has small corners. If a mask is used that has the shape of the designed structure, then rather than forming the designed structure with its sharp corners, an unacceptably distorted structure will be formed. To prevent this distortion, an odd looking OPC structure 2 is used as the mask. Due to complex diffraction effects, use of the OPC mask 2 results in the photoresist being exposed such that the hardened photoresist has a shape 3 that is closer to the desired shape 1.
Another problem often encountered occurs when imaging adjacent structures that have incompatible densities or pitches. FIG. 3 (Prior Art) is a simplified cross-sectional diagram that illustrates a set of features 4 having a pitch that is too fine to print. These features are shown in the bottom row of the diagram. This problem is solved by exposing the photoresist with multiple masks, where each mask has half the desired feature pitch or density. In FIG. 3, reference numerals 5 and 6 identify two such masks. For these reasons, many OPC masks and double exposure masks may be involved in a semiconductor process.
It is a general objective of semiconductor device manufacture to make the logic transistors smaller and smaller so that more logic transistors can be realized on an integrated circuit for a given cost of manufacture. If feature size is reduced, then the number of masks increases because multiple exposure steps are required. For example, to reduce feature size in a commercial high volume wafer fabrication facility from 45 nm to 20 nm, the number of mask steps was seen to increase from about thirty masks to as many as seventy masks. In one projected commercial semiconductor fabrication facility, a separate stepper will be used for each masking step so that the overall facility will have the desired wafer throughput. A fewer number of steppers could be used so that one stepper could be used to perform multiple masking steps, but then overall factory throughput would decrease.
A state of the art stepper of a type usable in a 20 nm process of the semiconductor fabrication facility described above may cost about 125 million dollars. Such a facility may require twenty-five steppers, making the cost of procuring wafer steppers a dominant cost of the entire fabrication facility. Making matters still worse, the number of steppers required is seen to increase with decreasing feature size. If feature size is to be reduced below 20 nm in the future, factory cost may be prohibitive.
To get around these problems, alternatives to conventional light photolithography have been proposed. These alternatives include: 1) extreme ultraviolet (EUV), 2) electron beam (e-beam), and 3) proton beam (p-beam) lithography. Making satisfactory EUV (soft X-ray) light sources is very challenging. The brightness and efficiency of EUV light sources are low. EUV stepper technology is still immature. FIG. 4 (Prior Art) is a diagram of an E-beam stepper. E-beam steppers are in experimental use but are generally only used for mask making and in pilot runs for research purposes. Both EUV and e-beam technologies can damage the underlying semiconductor wafer, and this damage may affect yield and reliability of the integrated circuits being manufactured.
P-beam lithography has been tried and has several benefits. Protons are large and heavy compared to electrons and do not travel very deeply into photoresist. As a result, protons generally do not damage the underlying wafer. When the protons strike the photoresist, they are slowed and create a cloud of slow speed collateral electrons. These slow speed collateral electrons in turn expose negative photoresist. As a result of this mechanism, a proton beam can expose a very small spot size thereby facilitating high resolution lithography. In positive photoresists, the proton beam breaks cross-linking bonds. Photoresists exist that are about one hundred times more sensitive to a proton beam than to an electron beam of the same energy. This increased sensitivity allows the use of less expensive photoresists as compared to the types of expensive photoresists used in e-beam lithography. Despite these advantages, attempts to commercialize p-beam technology have not been successful.
FIG. 5 (Prior Art) is a schematic illustration of a p-beam stepper that has a proton source 7. Protons emitted from this source 7 are then collimated by condenser optics 8 and are directed to an aperture and blanking plates 9. This breaks up the flow of protons into individual beams. The individual beams are then de-magnified with a 200× reduction 10 down to the wafer 11. It is very difficult to collimate protons because they are repelled from each other due their positive charges. This repulsion results in the protons separating from one another in the lateral dimension. Moreover, because the protons are initially produced by a hot ion source, the protons may have large initial lateral momentums. These effects result in serious focusing problems and make generating adequately collimated proton beams difficult.